Serial data word processing arrangement

ABSTRACT

A serial data word processing arrangement which can be used as a hand held security access control is disclosed. A microprocessor and electronically erasable and programmable red only memory chips (EEPROM), are used in a novel manner for storing security codes or other data resulting in a device that retains memory even after loss of power.

This invention concerns a serial data word processing arrangement ofmicroconstruction and, more particularly, it relates to an improvedserial data word processing arrangement of microconstruction forhandling a data word input having a predetermined number of binaryencoded bits and for either storing a data word input or comparing adata word input with a previously stored input.

BACKGROUND OF THE INVENTION

Various types of data processing arrangements have been designed in thepast. For example, U.S. Pat. No 4,128,900 to J. P. Lappington disclosesa programmable read only memory (PROM) for use with an electronic enginecontrol. The control is generally made up of a set of selected engineparameter sensors, a microprocessor, a programmed memory and aninput/output integrated circuit. The circuit correlates the inputs ofthe microprocessor and the set of parameter sensors so as to provide anoutput for precisely and timely controlling the output of the engineignition system for better engine performance. Since the engine controlis normally a single package for mass production auto manufacture, thecontrol has to be periodically modified to meet the performancerequirements of more than one engine. Accordingly the PROM isconnectable between th microprocessor and the programmed memory in orderto tailor the control in meeting the particular performance requirementsof an engine to which the control is installed. U.S. Pat. No. 4,514,798to W. Lesche et al. concerns a multimode control apparatus. Theapparatus is generally made up of a microprocessor, a programmablememory, an input/output unit, a pair of operator-settable parameters, aprocess monitor and a pair of manually operable mode-setting switches.Depending on the manner in which the pair of parameters are set, themicroprocessor and memory function to provide a controlled output to theapparatus being controlled. However, none of the aforediscussedreferences recognized the importance of providing an improved data wordprocessing arrangement for handling more than one data word input andfor providing a controlled output when a data word input compares with apreviously stored data word input.

In the use of data processing arrangements, it is advantageous toprovide a programmable data link for controlling one or more outputcomponents of the processing arrangement. In providing such control,e.g., security can be maximized and only certain components could beoperable depending on the particular encoding of the data word outputAccordingly, the improved data word processing arrangement isadvantageously of microconstruction and is comprised of a dual modemicroprocessor and an EEPROM. The microprocessor is capable of handlingany number of different encoded multibit data words that is only limitedby the memory capacity of the EEPROM. By reason of the EEPROM, oneseries of different data words can be stored then another, etc., so thatthe arrangement has maximum utilitv in storing and comparing data wordsin serving as a data control link for any data processing systemincluding any mechanism associated therewith.

SUMMARY OF THE INVENTION

An object of the invention is to provide an improved data wordprocessing arrangement of microconstruction that readily can beretrofitted into an existing data processing system.

Another object of the invention is to provide an improved data wordprocessing arrangement of microconstruction that can be used for storinga serial data input and for comparing stored data with a data input.

Still another object of the invention is to provide an improved dataword processing arrangement that can permanently store a variety of dataand compare the stored data with a data input and as the result of thecomparison for acceptance or rejection of the data input, the improvedarrangement serves as a data control link or security arrangement for adata processing system.

In summary, the improved serial data word processing arrangement isgenerally made up of a microprocessor and an electronically erasable andprogrammable read only memory device (EEPROM) operatively connected tothe microprocessor. Power supply means is connected to themicroprocessor for energizing the same. The microprocessor isadvantageously programmed for operating in either one of two modes, onefor storing a binary encoded data word input, and another for comparinga stored data word input with a data word input. An output is connectedto the microprocessor that can be used for indicating when a data wordinput compares with a stored data word input.

In order to minimize power requirements of the arrangement, energizationof the EEPROM is controlled by the microprocessor and is effected in anintermittent fashion when a data word is being stored or a stored dataword is being removed. The microprocessor is advantageously andpreferably programmed to handle a data word input made up of at least aplurality of three successive serial bytes with each byte being an 8-bitword and to divide up the plurality of bytes into a set of threeseparate single bytes for processing. During processing each byte isconverted into parallel format. Further, a data word input may alsoinclude a key pulse bit. In order to enable the arrangement to handlemore than one data word input for either storage or comparison with thestored data and to substantially use the memory capacity of the EEPROMan address means between the microprocessor and the EEPROM is providedwith a set of manually operable switch means for selecting more than onearea of the EEPROM for effecting either storing the plurality of threebytes of a given data word input or removing a stored data word inputfor comparison purposes with a data input.

In another embodiment of the data word processing arrangement anenhanced address means is provided between the microprocessor and theEEPROM operatively associated therewith. To this end, the address meansis comprised of a novel manually operable switch means for selectivelyconnecting a memory area of the EEPROM when a data word input is to bestored therein. Further, the enhanced address means directly connectsthe processor means to the EEPROM when a data word input of theprocessor means is compared (decoded) with all stored data word inputsof the EEPROM. One of the purposes of the decode mode is for identifyinga stored data word input of the EEPROM that compares with andcorresponds to a data word input of the processor means.

Other objects and advantages of the invention will become apparent whentaken in conjunction with the accompanying drawings and thespecification.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic view of an embodiment of the improved serialdata word processing arrangement of the invention.

FIG. 2 is another diagrammatic view similar to FIG. 1 with parts added,other parts rearranged and still other parts removed and furtherillustrates details of the invention.

FIG. 3 is a schematic view of a flow chart for an operative embodimentof the invention when it is in an encoding operative mode.

FIGS. 4A and 4B are schematic views of a flow chart for anotheroperative embodiment of the invention when it is in a decoding orcomparative mode.

FIG. 5 is a diagrammatic view similar to FIG. 1 and illustrates anotherembodiment of the improved serial data word processing arrangement.

FIG. 6 is a schematic view of a flow chart for an operative embodimentof the species of FIG. 5 when it is in a decoding operative mode.

DETAILED DESCRIPTION OF THE INVENTION

With further reference to FIG. 1, an improved serial data wordprocessing arrangement 10 is generally made up of a dual modemicroprocessor 12 and an electronically erasable and a programmable readonly memory (EEPROM) 14. An 8-bit parallel word input/output (I/O) databus 16 having eight leads interconnects the microprocessor and theEEPROM. By reason of three data I/O ports being located on one side ofthe EEPROM and five data I/O ports being located on the other sidethereof, data bus 16 is provided with branch portions 18 (having threeleads) and 20 (having five leads). A first address bus 22 having twoleads 23 and 25 interconnects the microprocessor and the EEPROM. Aselectively operable second address bus 24 is comprised of a set ofseven leads 26, 28, 30, 32, 34, 36 and 38. Five of the seven leads ofthe address bus 24 are connected to one side of EEPROM 14 while twoleads of the set of seven leads of address bus 24 are connected to theother side thereof all as evident in FIG. 1. Each lead 26, 28, 30, 32,34, 36 and 38 of bus 24 is provided with a series connected andselectively operable manual switch 40, 42, 44, 46, 48, 50, and 52.

Arrangement 10 is provided with an operative mode selector 54 and apower supply 56. An output lead 58 of selector 54 is connected toprocessor 12 as illustrated in FIG. 1. Power supply 56 is provided witha set of parallel interconnected output leads 60, 62, 64, 66 and 68 forenabling processor 12 during its use. Similarly, power supply 56 withits output 60 and set of parallel interconnected leads 70, 72 and 74 isconnected to EEPROM 14, and an input 76 for both second address bus 24and mode selector 54. Selector 54 is provided with a manually operableswitch 78 that is series connected between output 58 and input 76. Asrequired, a reset 80 is connected by an input lead 82 from supply 56 andis also connected by an output lead 84 to processor 12. A serial dataword input 86 is connected by an output lead 88 to processor 12. Theoscillator circuit of processor 12 is completed by a crystal-capacitorcircuit 90 as depicted in FIG. 1. An output of a suitable visual display92 is connected to processor 12 by a pair of output leads 94 and 96.Memory write and read only control leads 98 and 100 are connectedbetween processor 12 and EEPROM 14. An output lead 102 of processor 12is connected to EEPROM 14 for controlling the enablement of the EEPROMby supply 56 only when a data word input from input 86 is received byprocessor 12 for either encoding (storing) or decoding (comparing) witha prior stored data word input when arrangement 10 is used as willbecome more fully apparent hereinafter. It is to be understood, that theparticular manner in which processor 12 and EEPROM 14 are programmed andinterconnected by leads, data bus, address bus, etc. is believed to bewithin the appropriate skills of both a processor designer andprogrammer.

As further evident in FIG. 2, processor 12 is generally made up of anaccumulator 104 for receiving a multibit serial data word (stream) frominput 86. The data word is provided with a set of three successiveserial bytes 106, 108 and 110 with each byte being eight bits. The dataword is also provided with a bit location not shown) that serves as akey pulse for indicating that the serial data stream has been receivedby processor 12 for either encoding or decoding depending upon the modeselected for processor 12 by selector 54. Processor 12 is also comprisedof three registers 112, 114 and 116. As depicted in FIG. 2 duringoperation of processor 12 when a serial data word is received inaccumulator 104 each serial byte 106, 108 or 110 is first converted fromserial format to parallel format before each converted byte istransferred to its associated register 112, 114 or 116 respectively. Inother words, each byte 106, 108 or 110 of a data word input 86 isreceived in the accumulator-t is immediately outputted in parallelformat prior to the next byte of the data word input being received.Assuming that the processor is operating in the encoding mode, firstregister 112 transfers a parallel byte of an input to a data port of theprocessor as represented by element 118 for effecting transfer via databus 16 to a data port of EEPROM 14 as represented by element 120therein. After the first byte is transferred from processor 12 to EEPROM14 then the second and third parallel bytes of registers 114 and 116 arealso successively transferred in similar fashion to EEPROM.

These functions are accomplished by conventional software correspondingto the architecture of the particular microprocessor selected.

As further disclosed in FIG. 2, EEPROM 14 is provided with a memory 122that is divided up into eight storage areas designated zero throughseven (0 through 7) where each storage area stores a set of threeparallel bytes (e.g., the parallel converted series of three set bytes106, 108, and 110 of a set data stream). Assuming that all sevenswitches 40, 42, 44, 46, 48, 50 and 52 of address bus 24 are open theneach transferred parallel byte of a three-byte data stream is stored inits respective part of memory area designated zero. .On the other hand,if any switch of address bus 24 is closed, then each parallel byte of athree-byte data stream is stored in its respective part of thedesignated area of memory 122 associated with a given closed switch(e.g., operator closed switch 44 is associated with memory areadesignated 3). Hence, by reason of selective address bus 24 efficientutilization of the memory of EEPROM 14 is attained by arrangement 10during processor 12 use. It is noted here that the particular manner inwhich leads 72 and 102 are interconnected to memory 122 and theparticular manner in which leads 98 and 100 are connected to memory 122is believed to be within the skill of the art

In an operative embodiment of arrangement 10 for encoding a set dataword input, reference is made to the flow chart of FIG. 3. Processor 12is initialized by the operator by being connected to power supply 56 asindicated by "start" block 124. Then the operator leaves mode selectorswitch 78 in the open position as confirmed by block 126. At this timeprocessor 12 transmits a command signal via memory write control lead 98and also a signal via lead 102 for enabling EEPROM 14 by power supplyinput 72. As processor 12 cycles, decision block 128 will indicate whena key pulse has been received. As the first byte of a data input stream86 is received in accumulator 104 it is then unloaded in parallel formatto its associated register 112, see block 132. Similarly, as the secondand third bytes of the data input stream are timely and successivelyreceived in accumulator 104, they are each outputted in parallel formatand then loaded in their associated registers 114 and 116 before anotherbyte is received by the accumulator, steps 137 and 139. After the threebytes of a data stream are stored in their respective registers ofprocessor 12, each byte beginning with the first byte of a data streamis successively transferred from processor 12 via data bus 16 to EEPROM14 and a given area of memory 122 thereof as indicated by program blocks142, 144 and 146. Assuming that all switches of address bus 24 are open,then all three parallel bytes of a data stream would be stored in theirrespective parts of memory 122 at its area designated "0". On the otherhand, if any switch of bus 24 is closed, e.g., switch 48 is closed thenmemory area designated "5" would store all three bytes. As indicated byblock 148 the encoding routine is now ended until the next data streamis received in accumulator 104 during use of arrangement 10 in theencoding mode.

It is now assumed that mode selector switch 78 is closed therebyindicating to processor 12 to operate in the decode or stored data/datainput comparison mode as specified by blocks 152 and 154 of FIG. 4A. Inorder for processor 12 to compare a data input with stored data, theprocessor transmits a command signal via memory read control lead 100while at the same time it enables EEPROM 14 to be actuated by powersupply 56 by transmitting another command signal via lead 102. Assumingthat no switch of bus 24 is closed, then the stored bytes of a datastream in memory designated area "0" have been selected for comparison.Accordingly, each byte of a stored input is successively transferred(loaded) via data bus 16 to its associated first, second or thirdregister 112, 114 or 116 as indicated by blocks 156, 158 and 160. Inorder that each byte of a stored input is properly removed from itsrespective part of a designated memory area, processor 12 functions toprovide appropriate binary encoded signals via address bus 22 to memory122. Step 162 indicates when a data stream is received by processor 12via the key pulse thereof.

With the processor still in the decode mode as the set data stream inputis received by accumulator 104, a first 8-bit byte of the input isoutputted in parallel format and loaded in first register 112, asspecified by block 164. If the loaded 8-bit byte of the input compareswith a loaded 8-bit byte of the stored input as selected from EEPROM 14,then the routine continues (block 168). Otherwise the routine terminates(see step 172). A second 8-bit-byte of the set input is received byaccumulator 104, outputted in parallel format and loaded in secondregister 114 (step 170). If it compares with second addressed byte ofEEPROM 14 the routine continues as specified by block 176. Otherwise itis terminated (block 182). A third 8-bit byte input of the input isreceived and outputted by accumulator 104 then loaded into thirdregister 116 (step 178). If the third 8-bit byte input compares with thethird addressed input from EEPROM 14 the routine continues (block 180).Otherwise it terminates (block 184). If the data input compares with theaddressed stored input of EEPROM 14 then the input data stream is alsotested for a command bit signal as a part thereof. If such a command bitsignal occurs in the data input being compared, processor 12 providesoutput 92 with signals via leads 94 and 96 for indicating comparisonbetween an input and a stored input (block 186) thereby ending theroutine (block 188). It is noted here in addressing a stored input ofEEPROM 14 to be compared with an input, the memory area designated "0"would have its stored input unloaded unless one of the switches 40, 42,44, 46, 48, 50 or 52 is selected by the user. Assuming that the userfails to select a switch of bus 24, then the memory designated "0" ofEEPROM 14 would be unloaded as the result of signals from processor 12via leads 100 and 102. Further, address bus 22 via its binary encodedleads 23 and 25 progressively unloads each 8-bit byte from the memorydesignated area "0" in proper and successive fashion to its associatedregister 110, 112 and 114 all in following the first part of routine ofFIG. 4A, blocks 156, 158 and 160 as aforedescribed.

With reference to FIG. 5, a slightly modified arrangement 190 isprovided. It is to be understood that elements of arrangement 190 inFIG. 5 having the same reference numerals as elements of arrangement 10in FIGS. 1-2 are corresponding elements. Second address bus 192 ofarrangement 190 is comprised of a set of three leads 194, 196 and 198extending from processor 12. Second bus 192 is provided with first andsecond sets of selectively operable manual switches. The first set ofswitches is made up of three switches 200, 202 and 204. Thebridge-contact terminal of each switch 200, 202 and 204 is seriesconnected respectively to its associated lead 194, 196 and 198 of bus192. The second set of switches is a set of three switches 206, 208 and210. The bridge-contact terminal of each switch 206, 208 and 210 isseries connected to its associated lead 212, 214 and 216 of another setof three leads of bus 192 that is connected to EEPROM 14. The nonbridgecontact terminal of each switch 200 and 202 of the first set is parallelconnected by branch leads 218 and 220 to leads 216 and 214 respectivelyof the second set of three leads of bus 192. Nonbridge-contact terminalof switch 204 of the first set is directly connected to lead 212 of thesecond set of three leads of bus 192. Each nonbridge-contact terminal ofeach switch 206, 208, and 210 of the second set is parallel connected bythree branch leads to a common ground 222.

It is now assumed in the species of FIG. 5 that mode selector switch 54is in the open position for selecting the operative mode of processor 12to encode or store three parallel converted bytes of a set data input ina preselected memory area of EEPROM 14. To this end, the operatorselects all switches 200, 202 and 204 of the first set to be in the openposition. Then the operator selects any switch of the second set ofswitches 206, 208 and 210 to be either in the open or closed position.Depending on the selection for the second set of switches a particulararea of the memory of EEPROM 14 will be selected for storing theparallel data bytes of a data stream such as, e.g., memory designatedarea "4" of EEPROM 14 as shown in FIG. 2. As a data input stream isreceived by processor 12 in the species of FIG. 5 then theaforedescribed encoding routine of FIG. 3 will in effect be followed. Tothis end, leads 23 and 25 of address bus 22 will transmit binary encodedsignals for progressively storing each parallel 8-bit byte of the inputin proper fashion in its designated area of the memory of EEPROM 14.

On the other hand, when mode selector switch 78 is closed and processor12 of FIG. 5 is now in the decoding or data input/stored data comparisonmode, all switches 200, 202 and 204 of the first set are closed whileall switches 206, 208 and 210 of the second set are opened. Accordingly,each lead of the first set of leads 194, 196 and 198 of bus 192 aredirectly connected to its associated lead 216, 214 and 212 of the secondset of leads thereof. With reference to FIG. 6, the routine has beenstarted and the processor mode selected (see blocks 230 and 232). Asindicated by step 234, this part of the routine of FIG. 6 is the same asthe interim part of the routine of FIG. 3 as evidenced by blocks 128,130, 132, 137 and 139 and as aforedescribed. With a set data inputreceived and with each 8-bit byte of a set of three bytes outputted inparallel format and stored in their respective part of a designatedmemory area such as "0" the routine of FIG. 6 then checks to see if thedata input included a command signal and if so the routine continues bystoring the command signal in register four of the processor assubstantiated by blocks 236 and 238 or blocks 238 and 240 if no commandsignal.

Since address bus 192 is directly connected to EEPROM 14 throughinterconnected leads 194, 196 and 198; and 216, 214 and 212respectively, the processor via address buses 22 and 192 and data bus 16functions to search all eight memory areas (0-7) of the EEPROM, unloadeach loaded memory area in processor registers 112, 114 and 116 andcompare the unloaded bytes of each stored input from the EEPROM with itsassociated byte of a data input all in processor registers 112, 114 and116. If the loaded bytes of a given stored input fully compares with theloaded data input bytes then the sequence of blocks 240, 242 and 244occurs in FIG. 6. Otherwise routine termination occurs at a block 246,248 or 250 if no comparison is the result at any step 240, 242 or 244between the loaded input bytes of processor registers 112, 114 and 116and any stored input bytes of an encoded input loaded in the processorregisters. Assuming that full comparison occurs between a data input anda stored data input the register 4 of processor 12 functions with acommand signal registered therein to provide an output to element 92 assubstantiated by block 252 before the end of the routine (block 254).

Obviously many modifications and variations of the present invention arepossible in light of the above teachings. It is, therefore, to beunderstood that, within the scope of the appended claims, the inventionmay be practiced otherwise than as specifically described.

What is claimed is:
 1. A serial data EEPROM processing arrangementcomprising:a dual mode microprecessor comprising an accumulator and atleast 3 registers; means for inputting serial data in bytes of 8 bits orless to the accumulator of said dual mode microprocessor; means foroutputting parallel data from the registers of said dual modemicroprocessor; an elecrtonically erasable and programmable read onlymemory (EEPROM) electrically connected to said dual mode microprocessor;a data bus connecting the registers of said dual mode microprocessor tosaid EEPROM; an address bus interconnecting said dual modemicroprocessor with said EEPROM; a manually selectable address buscomprising switches to designate which area of the EEPROM is addressedby said dual mode microprocessor; means for manually switching saidmicroprocessor between an encoding and a decoding mode; and means foroutputting an electrical signal when the serial data inputted to saiddual mode microprocessor matches the data in said EEPROM.